RAM_DECOMP VHDL Example - RAM_DECOMP VHDL Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document_ID
UG901
Release_Date
2024-12-11
Version
2024.2 English
attribute ram_decomp : string;
attribute ram_decomp of myram : signal is "power";