FSM_SAFE_STATE Verilog Example - FSM_SAFE_STATE Verilog Example - 2024.2 English

FSM_SAFE_STATE Verilog Example - FSM_SAFE_STATE Verilog Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID

UG901

Release_Date

2024-12-11

Version

2024.2 English

(* fsm_safe_state = "reset_state" *) reg [7:0] my_state;