EXTRACT_RESET Verilog Example - EXTRACT_RESET Verilog Example - 2024.2 English

EXTRACT_RESET Verilog Example - EXTRACT_RESET Verilog Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID

UG901

Release_Date

2024-12-11

Version

2024.2 English

(* extract_reset = "yes" *) reg my_reg;