DSP_FOLDING_FASTCLOCK VHDL Example - DSP_FOLDING_FASTCLOCK VHDL Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID
UG901
Release_Date
2024-12-11
Version
2024.2 English
attribute dsp_folding_fastclock : string;
attribute dsp_folding_fastclock of clk_fast : signal is "yes";