DIRECT_ENABLE Verilog Example - DIRECT_ENABLE Verilog Example - 2024.2 English

DIRECT_ENABLE Verilog Example - DIRECT_ENABLE Verilog Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2024-12-11

Version

2024.2 English

(* direct_enable = "yes" *) input ena3;