ASYNC_REG Verilog Example - ASYNC_REG Verilog Example - 2024.2 English

ASYNC_REG Verilog Example - ASYNC_REG Verilog Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID

UG901

Release_Date

2024-12-11

Version

2024.2 English

(* ASYNC_REG = "TRUE" *) reg [2:0] sync_regs;