External RTL Traffic Generators using SV/Verilog - External RTL Traffic Generators using SV/Verilog - 2024.2 English

External RTL Traffic Generators using SV/Verilog - External RTL Traffic Generators using SV/Verilog - 2024.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID

UG1701

Release Date

2025-01-24

Version

2024.2 English

Generate traffic using the existing test bench written in the System Verilog/Verilog with slight modification to your test bench hierarchy, as explained below.