The hardware design that is based on Dynamic Function Exchange (DFX) technology comprises a static region and a reconfigurable partition spanning the AI Engine and PL. The static region contains IPs such as CIPS, NoC and memory, while the reconfigurable partition region is where the dynamic PL logic or the AI Engine and its associated PL logic can be placed.
Each Vitis linker run creates a reconfigurable module (RM) that can be loaded at runtime in the context defined by the static region. Refer to Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947) to understand the working of DFX design in more detail.
Settings for DFX based platform in Vivado
- Address Aperture Setting
- Setting the address range for the dynamic region is required so that the
CIPS and the SmartConnect can access kernels in the dynamic region after
linking stage by V++. Setting the apertures to DDR memory interfaces is
required to export the accessible DDR range for the kernel. Lock the
aperture settings by typing the following command in the Tcl
console.
set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /VitisRegion/PL_CTRL_S_AXI] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /VitisRegion/DDR_0] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /VitisRegion/DDR_1] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /VitisRegion/DDR_2] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /VitisRegion/DDR_3]
- Setup Block Design Container (BDC) for DFX
- Update Vitis Region BDC properties for DFX to freeze the boundary of this container and Enable Dynamic Function eXchange on this container. Configure Dynamic Function eXchange Wizard and add a configuration.
- Setup the DFX platforms properties
-
# Specify that this platform supports DFX set_property platform.uses_pr true [current_project] # Specify the dynamic region instance path for hardware run set_property platform.dr_inst_path {design_1_i/VitisRegion} [current_project] # Specify the dynamic region instance path for emulation set_property platform.emu.dr_bd_inst_path {design_1_wrapper_sim_wrapper/design_1_wrapper_i/design_1_i/VitisRegion} [current_project]
NoC stub is required in a DFX platform in Vitis Region to export memory interface for the platform. V++ linker can connect the PL kernel memory interfaces to the NoC stub to access memory.
- DFX Decoupler IP
- For security reasons, DFX platforms require the DFX decoupler IP to control the kernel during reconfiguration. This IP plays a crucial role in maintaining system integrity and preventing unexpected behavior.
- The DFX decoupler IP
-
- Turns off channels during reconfiguration: The decoupler disables communication channels during the reconfiguration process. This prevents any unintended requests from the static region that could lead to invalid AXI interface states or cause random toggles due to partial reconfiguration.
- Prevents unexpected side-effects: By isolating the static and reconfigurable regions, the decoupler avoids potential disruptions and side-effects in the static region caused by changes during reconfiguration.
- Enables XRT control: The Xilinx Runtime (XRT) automatically activates the DFX decoupler before initiating reconfiguration and deactivates it once the process is complete.
In essence, the DFX decoupler serves as a safeguard during reconfiguration, ensuring security and preventing unintended interactions between the static and reconfigurable regions of the DFX platform.
The end to end flow to create the DFX based design is detailed in the Vitis tutorial https://github.com/Xilinx/Vitis-Tutorials/tree/master/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX.
For more details on DFX design, refer to Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).