Notes - 2024.2 English - XD100

Simulation is NOT part and NOT demonstrated in this Tutorial!

xsa: CIPS settings are added manually; configured in the bd-files.

The example design is fully FAT-32

• if you like to use ext4 rootfs instead:

  • linux (Petalinux and Yocto) already generates it.

  • You will need to copy it to the Vitis platform in the [project-root]/Makefile in the bif section.

  • The v++ -package command line in [project-root]/vitis/Makefile will need adaptations to be able to use ext4 rootfs instead of FAT-32.

export ILA_EN := 1

• The ILA core connectivity is set up during v++ linking process loading the cfg file [project-root]/vitis/src/ila_0_bd.cfg and further configuration of ILA properties is managed in tcl file [project-root]/vitis/src/ila_0_def.tcl.

• Using the configuration file [project-root]/vitis/src/ila_0_bd.cfg allows the designer to mark AXI port for debug nets to and from the AIE engine for analysis.

• AFTER completing the vitis linking process execute the following:

  • [project-root]/vitis/build_hw/_x/link/vivado/vpl/prj $ vivado prj.xpr

  • Vivado: Open Implemented Design

  • Vivado: Tcl Console: write_debug_probes probe_0.ltx

  • Vivado: Close

  • [project-root]/vitis $ make update_ila

• A quick use case would be to validate the values of subtractor registers. After the probing file is loaded and the ILA is armed, rerunning ./aie_dly_test.exe a.xclbin will trigger the ILA capturing the signal values that should match those in the console.

root password is the one you have setup when using ssh/scp/… towards the board export TARGET := hw or hardware emulation export TARGET := hw_emu.