The diagram below summarizes the AI Engine resources used by the design. A total of 352 tiles are used for the combined functions of compute and local buffering. The $32 \times 6=192$ tiles implement the “row transforms” and “twiddle rotations” of the front-end portion of the design. The $32\times 5=160$ tiles implement the “column transforms” of the back-end portion of the design. A total of 352 AI Engine tiles is utilized by the design. A total of 256 PLIO stream resources transfer data between the AI Engine array and PL. Notice how careful floorplanning leads to a design that does not use additional overhead resources from the array.
The diagram below summarizes the PL resources used by the design. BRAM and URAM blocks provide the required storage to implement the “matrix transpose” operation sitting between the front-end and back-end AI Engine compute kernels. A modest amount of LUT and FF resources supports the design, including the PRBS generators & checkers. The PL design runs @ 520 MHz.