After the BD is complete and the design is validated, you must generate output products for synthesis and simulation, to integrate the BD into a top-level RTL design. The source files and the appropriate constraints for all the IP are generated and made available in the AMD Vivado™ Design Suite (IDE) Sources window.
Output files are generated for a BD based upon the Target Language that you specified during project creation, or in the Settings dialog box. If the source files for a particular IP cannot be generated in the specified target language a message displays in the Tcl Console.
- To generate output products, in the Vivado
IDE sources pane, right-click the BD and select Generate Output Products, as shown in the following figure.
Alternatively, click , as shown in the following figure.
- To generate the output product from the IP Sources tab, select and right-click
the BD, and select Generate Output Products from the
context menu as shown in the following figure.
Generating the output products generates the top-level netlist of the BD. The netlist is generated in the HDL language specified by the for the project.