Controlling the Phase, Frequency, Duty-Cycle, and Jitter of the Clock - Controlling the Phase, Frequency, Duty-Cycle, and Jitter of the Clock - 2024.1 English - UG949
UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)
Document_ID
UG949
Release_Date
2024-06-26
Version
2024.1 English
This section provides techniques for fine-tuning the clock characteristics.