Logic optimization ensures the most efficient logic design before attempting placement. It performs a netlist connectivity check to warn of potential design problems such as nets with multiple drivers and un-driven inputs. Logic optimization also performs block RAM power optimization.
Often design connectivity errors are propagated to the logic optimization step where the flow fails. It is important to ensure valid connectivity using DRC Reports before running implementation.
Logic optimization skips optimization of cells and nets that have DONT_TOUCH
properties set to a value of TRUE. Logic optimization also skips optimization of design
objects that have directly applied timing constraints and exceptions. This prevents
constraints from being lost when their target objects are optimized away from the
design. Logic optimization also skips optimization of design objects that have physical
constraints such as LOC, Bel, RLOC, LUTNM HLUTNM ASYNC_REG, and LOCK_PINS. An Info
message at the end of each optimization stage provides a summary of the number of
optimizations prevented due to constraints. Specific messages about which constraint
prevented which optimizations can be generated with the -debug_log switch.
The Tcl command used to run Logic Optimization is opt_design.