Verilog Meta Comments - 2024.1 English - UG901

• Verilog meta comments are understood by the Verilog parser.
• Verilog meta comments set constraints on individual objects, such as:
  • Module
  • Instance
  • Net
• Verilog meta comments set directives on synthesis:
  • parallel_case and full_case
  • translate_on and translate_off
  • All tool specific directives (for example, syn_sharing)