VHDL Example on Architecture - VHDL Example on Architecture - 2024.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID
UG901
Release_Date
2024-06-28
Version
2024.1 English
architecture rtl of test is
attribute dont_touch : string;
attribute dont_touch of rtl : architecture is "yes";