Table 1. VHDL-2008 RESERVED Words
| abs |
access |
after |
alias |
| all |
and |
architecture |
array |
| assert |
assume |
assume_+guarantee |
attribute |
| begin |
block |
body |
buffer |
| bus |
case |
component |
configuration |
| constant |
context |
cover |
default |
| disconnect |
downto |
else |
elsif |
| end |
entity |
exit |
fairness |
| file |
for |
force |
function |
| generate |
generic |
group |
guarded |
| if |
impure |
in |
inertial |
| inout |
is |
label |
library |
| linkage |
literal |
loop |
map |
| mod |
nand |
new |
next |
| nor |
not |
null |
of |
| on |
open |
or |
others |
| out |
package |
parameter |
port |
| postponed |
procedure |
process |
property |
| protected |
pure |
range |
record |
| register |
reject |
release |
rem |
| report |
restrict |
restrict_guarantee |
return |
| rol |
ror |
select |
sequence |
| severity |
signal |
shared |
sla |
| sll |
sra |
srl |
strong |
| subtype |
then |
to |
transport |
| type |
unaffected |
units |
until |
| use |
variable |
vmode |
vprop |
| vunit |
wait |
when |
while |
| with |
xnor |
xor |
|