Using Synthesis Settings - 2024.1 English

The Settings dialog box opens, as shown in the following figure:

Physical constraints

These constraints define pin placement and absolute, or relative, placement of cells such as block RAMs, LUTs, Flip-Flops, and device configuration settings.

Timing constraints

These constraints define the frequency requirements for the design. Without timing constraints, the Vivado Design Suite optimizes the design solely for wire length and placement congestion.

See Vivado Design Suite User Guide: Using Constraints (UG903) for more information about organizing constraints.

New runs use the selected constraint set, and the Vivado synthesis targets this constraint set for design changes.

You can also define your own strategy. When you select a synthesis strategy, the available Vivado strategy displays in the dialog box. You can override synthesis strategy settings by changing the option values described in Creating Run Strategies.

For a list of all the strategies and their respective settings, see the directive option in the following list and see Vivado Preconfigured Strategies to see a matrix of strategy default settings.

flatten_hierarchy

Determines how Vivado synthesis controls hierarchy.

none

Instructs the synthesis tool to never flatten the hierarchy. The output of synthesis has the same hierarchy as the original RTL.

full

Instructs the tool to fully flatten the hierarchy leaving only the top level.

rebuilt

When set, rebuilt allows the synthesis tool to flatten the hierarchy, perform synthesis, and rebuild the hierarchy based on the original RTL. This value allows the QoR benefit of cross-boundary optimizations, with a final hierarchy that is similar to the RTL for ease of analysis.

gated_clock_conversion

Turns on and off the ability of the synthesis tool to convert the clocked logic with enables.

The use of gated clock conversion also requires using an RTL attribute to work. See GATED_CLOCK, for more information.

bufg

Controls how many BUFGs the tool infers in the design. The Vivado design tools use this option when other BUFGs in the design netlists are not visible to the synthesis process.

The tool infers up to the amount specified, and tracks how many BUFGs are instantiated in the RTL. For example, if the -bufg option is set to 12, and there are three BUFGs instantiated in the RTL, the Vivado synthesis tool infers up to nine more BUFGs.

directive

Replaces the -effort_level option. When specified, this option runs Vivado synthesis with different optimizations. See Vivado Preconfigured Strategies for a list of all strategies and settings. Values are:

Default

Default settings. See Vivado Preconfigured Strategies.

RuntimeOptimized

Performs fewer timing optimizations and eliminates some RTL optimizations to reduce synthesis runtime.

AreaOptimized_high

Performs general area optimizations, including forcing ternary adder implementation, applying new thresholds for using carry chain in comparators, and implementing area-optimized multiplexers.

AreaOptimized_medium

Performs general area optimizations, including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into block RAM, applying lower thresholds for use of CARRY chain in comparators, and also area optimized MUX operations.

AlternateRoutability

Set of algorithms to improve route-ability (less use of MUXFs and CARRYs)

AreaMapLargeShiftRegToBRAM

Detects large shift registers and implements them using dedicated block RAM.

AreaMultThresholdDSP

Lower threshold for dedicated DSP block inference.

FewerCarryChains

Higher operand size threshold to use LUTs instead of the carry chain.

LogicCompaction

Arranges CARRY chains and LUTs in such a way that it makes the logic more compact using fewer SLICES. This could have a negative effect on timing QoR.

PerformanceOptimized

Performs general timing optimizations, including logic level reduction at the expense of area.

PowerOptimized_high

Performs general timing optimizations including logic level increase at the expense of area.

PowerOptimized_medium

Performs general timing optimizations by lowering logic level reduction at the expense of area.

global_retiming

devices only. For controlling retiming select the -global_retiming option. This option <auto|on|off> provides an option to perform for intra-clock sequential paths by automatically moving registers (register balancing) across combinatorial gates or LUTs. It maintains the original behavior and latency of the circuit and does not require changes to the RTL sources. The default is auto. For Versaldevices retiming will performed when auto is set. For non-Versaldevices, retiming will not be performed when auto is set.

Note: When retiming in OOC mode, registers that are driven by or that are driving ports are not retimed.

fsm_extraction

Controls how synthesis extracts and maps finite state machines. FSM_ENCODING describes the options in more detail.

keep_equivalent_registers

Prevents merging of registers with the same input logic.

resource_sharing

Sets the sharing of arithmetic operators between different signals. The values are auto, on, and off. The auto value sets performing resource sharing depend on the timing of the design.

control_set_opt_threshold

Sets the threshold for the clock to enable optimization to the lower number of control sets. The default is auto which means the tool chooses a value based on the device being targeted. Any positive integer value is supported.

The given value is the number of fanouts necessary for the tool to move the control sets into the D logic of a register. If the fanout is higher than the value, the tool attempts to have that signal drive the control_set_pin on that register.

no_lc

When checked, this option turns off LUT combining.

no_srlextract

When checked, this option turns off SRL extraction for the full design so that they are implemented as simple registers.

shreg_min_size

Is the threshold for inference of SRLs. The default setting is 3. This sets the number of sequential elements that would result in the inference of an SRL for fixed delay chains (static SRL). Strategies define this setting as 5 and 10 also. See Vivado Preconfigured Strategies for a list of all strategies and settings.

max_bram

Describes the maximum number of block RAM allowed in the design. Often this is used when there are black boxes or third-party netlists in the design and allow the designer to save room for these netlists.

Note: The default setting of -1 indicates that the tool chooses the maximum number allowed for the specified part.

max_uram

Sets the maximum number of UltraRAM (AMD UltraScale+™ device block RAMs) blocks allowed in design. The default setting of -1 indicates that the tool chooses the maximum number allowed for the specified part.

max_dsp

Describes the maximum number of block DSP allowed in the design. Often this is used when there are black boxes or third-party netlists in the design and allows room for these netlists. The default setting of -1 indicates that the tool chooses the maximum number allowed for the specified part.

max_bram_cascade_height

Controls the maximum number of block RAM that can be cascaded by the tool. The default setting of -1 indicates that the tool chooses the maximum number allowed for the specified part.

max_uram_cascade_height

Controls the maximum number of UltraScale+ device UltraRAM blocks that can be cascaded by the tool. The default setting of -1 indicates that the tool chooses the maximum number allowed for the specified part.

cascade_dsp

Controls how adders in sum DSP block outputs are implemented. By default, the sum of the DSP outputs is computed using the block built-in adder chain. The value tree forces the sum to be implemented in the fabric. The values are auto, tree, and force. The default is auto.

no_timing_driven

(Optional) Disables the default timing-driven synthesis algorithm. This results in a reduced synthesis runtime, but ignores the effect of timing on synthesis.

sfcu

Run synthesis in single-file compilation unit mode.

assert

Enable VHDL assert statements to be evaluated. A severity level of failure or error stops the synthesis flow and produces an error. A severity level of warning generates a warning.

debug_log

Prints out extra information in the synthesis log file for debugging purposes. The -debug_log should be added to the More Options field.

• The tcl.pre and tcl.post options are hooks for Tcl files that run immediately before and after synthesis.
  Note: Paths in the tcl.pre and tcl.post scripts are relative to the associated run directory of the current project: <project>/<project.runs>/<run_name>.

  See Vivado Design Suite User Guide: Using Tcl Scripting (UG894) for more information about Tcl scripting.

  Use the DIRECTORY property of the current project or current run to define the relative paths in your scripts.