Supported Generate Statements - Supported Generate Statements - 2024.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID
UG901
Release_Date
2024-06-28
Version
2024.1 English

Vivado synthesis supports all Behavioral Verilog generate statements:

  • generate-loop (generate-for)
  • generate-conditional (generate-if-else)
  • generate-case (generate-case)