FSM_SAFE_STATE - 2024.1 English - UG901

FSM_SAFE_STATE instructs Vivado synthesis to insert logic into the state machine that detects there is an illegal state, puts it into a known, good state on the next clock cycle.

For example, if there were a state machine with a "one_hot" encode, and that is in a "0101" state (which is an illegal for "one_hot" ), the state machine would be able to recover. Place the FSM_SAFE_STATE attribute on the state machine registers. You can set this attribute in either the RTL or in the XDC.

The legal values for FSM_SAFE_STATE are:

auto_safe_state

Uses Hamming-3 encoding for auto-correction for one bit/flip.

reset_state

Forces the state machine into the reset state using Hamming-2 encoding detection for one bit/flip.

power_on_state

Forces the state machine into the power-on state using Hamming-2 encoding detection for one bit/flip.

default_state

Forces the state machine into the default state specified in RTL: the state that is specified in default branch of the case statement in Verilog or the state specified in the others branch of the case statement in VHDL. For this to work, a default or others state must be in the RTL.