VHDL Instantiation Unit - 2024.1 English - UG900

When a VHDL design instantiates a component, the xelab command treats the component name as a VHDL unit and searches for it in the logical work library.

• If a VHDL unit is found, the xelab command binds it and the search stops.
• If xelab does not find a VHDL unit, it treats the case-preserved component name as a Verilog module name and continues a case-sensitive search in the user-specified list and order of unified logical libraries. The command selects the first matching the name, then stops the search.
• If case sensitive search is not successful, xelab performs a case-insensitive search for a Verilog module in the user-specified list and order of unified logical libraries. If a unique binding is found for any one library, the search stops.