Step 1: Analyzing the Design File - 2024.1 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

To begin, analyze your HDL source files by type, as shown in the following table. Each command can take multiple files.

Table 1. File Types and Associated Commands for Design File Analysis
File Type Command
Verilog xvlog <VerilogFileName(s)>
SystemVerilog xvlog -sv <SystemVerlilogFileName(s)>
VHDL xvhdl <VhdlFileName(s)>