Programs running on MicroBlaze V use effective addresses to access a flat 4 GB address space with the 32-bit implementation (RV32), and up to a 16 EB address space with the 64-bit implementation (RV64) depending on parameter C_ADDR_SIZE.
The processor can interpret this address space in different ways, depending on the virtual memory system as defined in the RISC-V Instruction Set Manual, Volume II:
- In bare mode, effective addresses are used to directly access physical memory.
- In virtual mode, the effective addresses are translated into physical addresses by the virtual-memory management hardware in the processor.
Virtual mode provides system software with the ability to relocate programs and data anywhere in the physical address space. System software can move inactive programs and data out of physical memory when space is required by active programs and data.
Relocation can make it appear to a program that more memory exists than is actually implemented by the system. This frees the programmer from working within the limits imposed by the amount of physical memory present in a system. Programmers do not need to know which physical-memory addresses are assigned to other software processes and hardware devices. The addresses visible to programs are translated into the appropriate physical addresses by the processor.
Virtual mode provides greater control over memory protection. Memory pages can be individually protected from unauthorized access. Protection and relocation enable system software to support multitasking. This capability gives the appearance of simultaneous or near-simultaneous execution of multiple programs.
In MicroBlaze V, virtual mode is implemented by the memory-management unit (MMU), available when C_USE_MMU is set to 3 (Supervisor). The MMU controls physical-address mapping and supports memory protection. Using these capabilities, system software can implement demand-paged virtual memory and other memory management schemes.
MicroBlaze V supports the RISC-V Supervisor Level ISA, with the Sv32 page-based virtual-memory system for the 32-bit implementation, and the Sv39 page-based virtual-memory system for the 64-bit implementation. In both cases, the Supervisor Address Translation and Protection (satp) register implements a 7-bit address space identifier (ASID).