The MicroBlaze V processor core exports a number
of internal signals for trace purposes. This signal interface is not standardized and
new revisions of the processor might not be backward compatible regarding signal
selection or functionality. It is recommended that you not design custom logic for these
signals, but rather use them using analysis IP provided by AMD Adaptive
Computing. The trace signals are grouped in the TRACE bus. The current
set of trace signals is listed in the following table.
| Signal Name | Description | VHDL Type |
|---|---|---|
| Trace_Valid_Instr | Valid instruction on trace port | std_logic |
| Trace_Instruction 1 | Instruction code | std_logic_vector (0 to 31) |
| Trace_PC 1 | Program counter, where N = 32 - 64, determined by parameter C_ADDR_SIZE for 64-bit MicroBlaze V, and 32 otherwise | std_logic_vector (0 to N-1) |
| Trace_Reg_Write 1 | Instruction writes to the register file | std_logic |
| Trace_FP_Reg_Write 1 | Instruction writes to the FPU register file | std_logic |
| Trace_Reg_Addr 1 | Destination register address | std_logic_vector (0 to 4) |
| Trace_PID_Reg 1 | Address Space Identifier (ASID) | std_logic_vector (0 to 7) |
| Trace_New_Reg_Value 1 | Destination register update value, where N = C_DATA_SIZE | std_logic_vector (0 to N-1) |
| Trace_Exception_Taken 1 | Instruction result in taken exception | std_logic |
| Trace_Exception_Kind 1, 2 | Exception type. The description for the exception type is documented below. | std_logic_vector (0 to 5) |
| Trace_Jump_Taken 1 | Jump instruction or branch instruction evaluated true, that is taken | std_logic |
| Trace_Jump_Hit 1, 5 | Branch target cache hit | std_logic |
| Trace_Jump_Mispredict 1, 5 | Branch target cache mispredict | std_logic |
| Trace_Data_Access 1 | Valid D-side memory access | std_logic |
| Trace_Data_Address 1 | Address for D-side memory access, where N = 32 - 64, determined by parameter C_ADDR_SIZE | std_logic_vector (0 to N-1) |
| Trace_Data_Write_Value 1 | Value for D-side memory write access, where N = C_DATA_SIZE | std_logic_vector (0 to N-1) |
| Trace_Data_Byte_Enable 1 |
Byte enables for D-side memory access, where N = C_DATA_SIZE / 8 |
std_logic_vector (0 to N-1) |
| Trace_Data_Read 1 | D-side memory access is a read | std_logic |
| Trace_Data_Write 1 | D-side memory access is a write | std_logic |
| Trace_DCache_Req | Data memory address is within D-Cache range. Set when a memory access instruction is executed. | std_logic |
| Trace_DCache_Hit | Data memory address is present in D-Cache. Set simultaneously with Trace_DCache_Req when a cache hit occurs. | std_logic |
| Trace_DCache_Rdy | Data memory address is within D-Cache range and the access is completed. Only set following a request with Trace_DCache_Req = 1 and Trace_DCache_Hit = 0. | std_logic |
| Trace_DCache_Read | The D-Cache request is a read. Valid only when Trace_DCache_Req = 1. | std_logic |
| Trace_ICache_Req | Instruction memory address is within I-Cache range, and the cache is enabled in the Machine Status register. Set when an instruction is read into the instruction prefetch buffer. | std_logic |
| Trace_ICache_Hit | Instruction memory address is present in I-Cache. Set simultaneously with Trace_ICache_Req when a cache hit occurs. | std_logic |
| Trace_ICache_Rdy |
|
std_logic |
| Trace_OF_PipeRun | Pipeline advance for Decode stage | std_logic |
| Trace_EX_PipeRun 3 | Pipeline advance for Execution stage | std_logic |
| Trace_MEM_PipeRun 3, 4 | Pipeline advance for Memory stage | std_logic |
| Trace_Privilege_Mode | Current privilege mode:
|
std_logic_vector(0 to 1) |
| Trace_Halted | Pipeline is halted by debug | std_logic |
|
||
The used Trace exception types are listed in the following table. All unused Trace exception types are either reserved or unimplemented.
| Trace_Exception_Kind | Description |
|---|---|
| 000000 | Instruction address misaligned |
| 000001 | Instruction access fault |
| 000010 | Illegal instruction |
| 000011 | Breakpoint |
| 000100 | Load address misaligned |
| 000101 | Load access fault |
| 000110 | Store/AMO address misaligned |
| 000111 | Store/AMO access fault |
| 001000 | Environment call from U-mode |
| 001001 | Environment call from S-mode |
| 001101 | Environment call from M-mode |
| 001100 | Instruction page fault |
| 001101 | Load page fault |
| 001111 | Store/AMO page fault |
| 011000 | FSL exception |
| 100000 | Non-maskable interrupt |
| 101101 | External interrupt |
| 110000 | External Break |