The stvec register is a read/write register that holds trap vector
configuration, consisting of a vector base address (BASE) and a read-only vector
mode (MODE). The register only exists when supervisor mode is enabled (C_USE_MMU > 2).
Figure 1. Supervisor Trap-Vector Base-Address Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 31:2 | BASE | Vector base address | (C_BASE_VECTORS + 4) / 4 |
| 1:0 | MODE | Direct: All traps set PC to BASE. Read only. | 00 |
Because MODE is read-only zero, the supervisor trap handler code must be aligned on a 32-bit word boundary.
With compressed instructions enabled (C_USE_COMPRESSION > 0), software must use an align attribute to
ensure this is the case.
With the RISC-V GCC compiler, this can be achieved with the following
code:
/* Ensure alignment on a word boundary */
void trap_handler(void) __attribute__((aligned(4)));