The scause register is a read/write register. When a trap is taken
into S-mode, scause is written with a code indicating the event that caused the
trap. The register only exists when supervisor mode is enabled (C_USE_MMU > 2).
The code uses four bits, unless extended AXI4-Stream custom instructions with exception support are enabled
(C_FSL_LINKS > 0, C_EXTENDED_FSL_INSTR > 0, and C_FSL_EXCEPTION > 0), in which case it uses five bits.
Figure 1. Supervisor Cause Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 63, 31 | Interrupt | Set if the trap was caused by an interrupt | 0 |
| 4:0, 3:0 | Code | Contains a code identifying the last exception or interrupt | 00000, 0000 |
The processor supported interrupt and exception codes are listed in the description of the Machine Cause register.