Read and Write Data Steering - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

The MicroBlaze V data-side bus interface performs the read steering and write steering required to support the following transfers:

  • Byte, half word, and word transfers to word devices
  • Byte and half word transfers to half word devices
  • Byte transfers to byte devices

MicroBlaze V does not support transfers that are larger than the addressed device. These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the bus interface. Data steering for read and write cycles are shown in the following tables.

Table 1. Read Data Steering (Load to Register xD)
Address Byte Enable Transfer Size Register xD Data
xD[31:24] xD[23:16] xD[15:8] xD[7:0]
11 1000 byte       Byte0
10 0100 byte       Byte1
01 0010 byte       Byte2
00 0001 byte       Byte3
10 1100 halfword     Byte0 Byte1
00 0011 halfword     Byte2 Byte3
00 1111 word Byte0 Byte1 Byte2 Byte3
Table 2. Write Data Steering (Store from Register xD)
Address Byte Enable Transfer Size Write Data Bus Bytes
Byte 3 Byte 2 Byte 1 Byte 0
11 1000 byte xD[7:0]      
10 0100 byte   xD[7:0]    
01 0010 byte     xD[7:0]  
00 0001 byte       xD[7:0]
10 1100 halfword xD[15:8] xD[7:0]    
00 0011 halfword     xD[15:8] xD[7:0]
00 1111 word xD[31:24] xD[23:16] xD[15:8] xD[7:0]
Note: Other masters could have more restrictive requirements for byte lane placement than those allowed by MicroBlaze V. Slave devices are typically attached “left-justified” with byte devices attached to the most significant byte lane, and half word devices attached to the most significant half word lane. The MicroBlaze V steering logic fully supports this attachment method.