Protocol Compliance - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)

Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English
The MicroBlaze V instruction cache interface issues the following subset of the possible ACE transactions.
ReadClean
Issued when a cache line is allocated.
ReadOnce
Issued when the cache is off.

The MicroBlaze data cache interface issues the following subset of the possible ACE transactions:

ReadClean
Issued when a cache line is allocated.
CleanUnique
Issued when an SC instruction is executed as part of an exclusive access sequence.
ReadOnce
Issued when the cache is off.
WriteUnique
Issued whenever a store instruction performs a write.
CleanInvalid
Issued when an external cache flush is executed.
MakeInvalid
Issued when an external cache invalidate is executed.

Both interfaces issue the following subset of the possible distributed virtual memory (DVM) transactions:

DVM Operation
Branch Predictor Invalidate
L branch predictor invalidate all.
Physical Instruction Cache Invalidate
Non-secure physical instruction cache invalidate by PA without virtual index.
Virtual Instruction Cache Invalidate
Hypervisor invalidate by VA.
DVM Sync
Synchronization.
DVM Complete
Completion.

In addition to the DVM transactions above, the interfaces only accept the CleanInvalid and MakeInvalid transactions. These transactions have no effect in the instruction cache, and invalidate the indicated data cache lines. If any other transactions are received, the behavior is undefined. Only a subset of AXI4 transactions are used by the interfaces, as described in Cache Interfaces.