A machine external break platform interrupt is performed by asserting the
external break signal (that is, the Ext_BRK input
port). On a break, the instruction in the execution stage completes while the
instruction in the decode stage is replaced by a branch to the trap-vector base-address
in mtvec.
The return address (the PC associated with the instruction in the decode stage at the time of the break) is automatically loaded into mepc. The mcause interrupt bit is set to 1 and the exception code is set to 16.
A platform interrupt is only handled when the global interrupt enable bit MIE in mstatus is set to 1 (that is, there is no other interrupt in progress).
The Ext_BRK signal must be kept asserted until the trap has occurred,
and deasserted before the MRET instruction is executed.
Equivalent Pseudocode
mepc ← PC
PC ← mtvec
mcause ← 0x80000010
mstatus.mpie ← mstatus.mie
mstatus.mie ← 0
if C_USE_MMU > 0
mstatus.mpp ← privilege mode
else
mstatus.mpp ← 11
mtval ← 0
Reservation ← 0