Description
MicroBlaze V writes the value from
register rs1 to the link x interface. If the available number of links set by
C_FSL_LINKS is less than or equal to x, link 0
is used.
The PUT instruction has 16 variants.
The blocking versions (when n is 0) stall until there is space available in the interface. The non-blocking versions do not stall, and set the C bit in mstream to 0 if space is available, and to 1 if no space is available.
All data PUT instructions (when c is 0) set the control bit to the interface to 0. All control PUT instructions (when c is 1) set the control bit to 1.
The test versions (when the t bit is 1) are handled as normal, except that the write signal to the link is not asserted, and therefore no source register is required. The test version requires that rs1 is x0.
The atomic versions (when the a bit is 1) cannot be interrupted by a machine external interrupt or external break. Each atomic instruction prevents the subsequent instruction from being interrupted. This means that a sequence of atomic instructions can be grouped together without an interrupt breaking the program flow.
Pseudocode
if x >= C_FSL_LINKS then
x ← 0
Mx_AXIS_TDATA ← (rs1)
if n = 1 then
mstream.C ← Mx_AXIS_TVALID ˄ Mx_AXIS_TREADY
Mx_AXIS_TLAST ← c
Registers Altered
mstreamLatency
- One cycle with
C_OPTIMIZATION= 0, 2, 3 - Two cycles with
C_OPTIMIZATION= 1
The blocking versions of this instruction stall the pipeline until the
instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the
instruction is not atomic.
Notes
- These instructions are only available when the parameter
C_FSL_LINKSis greater than 0. - The extended instructions (test and atomic versions) are only
available when the parameter
C_USE_EXTENDED_FSL_INSTRis set to 1.