MicroBlaze V Core Configurability - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

The MicroBlaze V core has been developed to support a high degree of user configurability. This allows tailoring of the processor to meet specific cost/performance requirements.

Configuration is done using parameters that typically enable, size, or select certain processor features. For example, the instruction cache is enabled by setting the C_USE_ICACHE parameter. The size of the instruction cache, and the cacheable memory range, are all configurable using: C_ICACHE_BYTE_SIZE, C_ICACHE_BASEADDR, and C_ICACHE_HIGHADDR respectively.

Parameters valid for the latest version of MicroBlaze V are listed in the following table. The configurability is fully backward compatible.

Table 1. Configuration Parameters
Parameter Name Feature/Description Allowable Values Default Value Tool Assigned VHDL Type
C_FAMILY Target family See below virtex7 Yes String
C_DATA_SIZE Data size:
  • 32 = rv32i
  • 64 = rv64i
 32, 64 32   Integer
C_ADDR_SIZE Address Size 32-64 32 NA Integer
C_OPTIMIZATION Select implementation optimization:
  • 0 = Performance
  • 1 = Area
  • 2 = Frequency
  • 3 = Throughput
 0, 1, 2, 3 0   Integer
C_INTERCONNECT Select interconnect:
  • 2 = AXI4 only
  • 3 = AXI4, ACE
 2, 3 2   Integer
C_BASE_VECTORS 1 Configurable base vectors 0x0 - 0xFFFFFFFF FFFFFFFF 0x0   std_logic_vector
C_FAULT_TOLERANT Implement fault tolerance 0, 1 0 Yes Integer
C_ECC_USE_CE_EXCEPTION Generate exception for correctable ECC error 0, 1 0   Integer
C_LOCKSTEP_SLAVE Lockstep Slave 0, 1 0   Integer
C_AVOID_PRIMITIVES Disallow FPGA primitives:
  • 0 = None
  • 1 = SRL
  • 2 = LUTRAM
  • 3 = Both
 0, 1, 2, 3 0   Integer
C_ENABLE_DISCRETE_PORTS Show discrete ports 0, 1 0   Integer
C_INSTANCE Instance Name Any instance name microblaze_v Yes String
C_D_AXI Data side AXI interface 0, 1 0   Integer
C_D_LMB Data side LMB interface 0, 1 1   Integer
C_I_AXI Instruction side AXI interface 0, 1 0   Integer
C_I_LMB Instruction side LMB interface 0, 1 1   Integer
C_LMB_DATA_SIZE LMB interface data size 32, 64 32   Integer
C_USE_BARREL Barrel shifter implementation:
  • 1 = Performance
  • 2 = Area
 1, 2 1   Integer
C_USE_MULDIV Include hardware multiplier and divider:
  • 0 = None
  • 1 = Normal
  • 2 = Smart
 0, 1, 2 0   Integer
C_USE_FPU Include hardware floating-point unit:
  • 0 = None
  • 1 = Single
 0, 1 0   Integer
C_USE_ATOMIC Include atomic instructions 0, 1 0   Integer
C_USE_COMPRESSION Use compressed instructions 0, 1 0   Integer
C_USE_BITMAN_A Use bit manipulation instructions (Zba extension) 0, 1 0   Integer
C_USE_BITMAN_B Use bit manipulation instructions (Zbb extension) 0, 1 0   Integer
C_USE_BITMAN_C Use bit manipulation instructions (Zbc extension) 0, 1 0   Integer
C_USE_BITMAN_S Use bit manipulation instructions (Zbs extension) 0, 1 0   Integer
C_USE_COUNTERS Enable base counters and timers 0, 1 1   Integer
C_MISALIGNED_EXCEPTIONS Enable exception handling for misaligned exceptions 0, 1 1   Integer
C_ILL_INSTR_EXCEPTION Enable exception handling for illegal instructions:
  • 0 = None
  • 1 = Basic
  • 2 = Complete
 0, 1, 2 2   Integer
C_M_AXI_I_BUS_EXCEPTION Enable exception handling for M_AXI_I bus error 0, 1 1   Integer
C_M_AXI_D_BUS_EXCEPTION Enable exception handling for M_AXI_D bus error 0, 1 1   Integer
C_FSL_EXCEPTION Enable exception handling for stream links 0,1 0   Integer
C_IMPRECISE_EXCEPTIONS Allow imprecise exceptions 0, 1 0   Integer
C_DEBUG_ENABLED MDM Debug interface:
  • 0 = None
  • 1 = Basic
 0,1 1   Integer
C_NUMBER_OF_PC_BRK Number of hardware breakpoints 0-8 1   Integer
C_NUMBER_OF_RD_ADDR_BRK Number of read address triggers 0-4 0   Integer
C_NUMBER_OF_WR_ADDR_BRK Number of write address triggers 0-4 0   Integer
C_DEBUG_EVENT_COUNTERS Hardware performance monitor event counters 0 - 32 0   Integer
C_DEBUG_LATENCY_COUNTERS Hardware performance monitor latency counters 0 - 16 0   Integer
C_DEBUG_COUNTER_WIDTH Hardware performance monitor counter width 32, 48, 64 64   Integer
C_DEBUG_INTERFACE Debug Interface:
  • 0 = Debug Serial
  • 1 = Debug Parallel
  • 2 = AXI4-Lite
0,1,2 0   Integer
C_ASYNC_INTERRUPT Asynchronous Interrupt 0,1 0 Yes Integer
C_ASYNC_WAKEUP Asynchronous Wakeup 00,01,10,11 00 Yes Integer
C_INTERRUPT_IS_EDGE Level/edge interrupt 0, 1 0 Yes Integer
C_EDGE_IS_POSITIVE Negative/positive edge interrupt 0, 1 1 Yes Integer
C_FSL_LINKS Number of AXI4-Stream interfaces 0 -16 0   Integer
C_USE_EXTENDED_FSL_INSTR Enable use of extended stream instructions 0, 1 0   Integer
C_ICACHE_BASEADDR Instruction cache base address 0x0 - 0xFFFFFFFF FFFFFFFF 0x0   std_logic_vector
C_ICACHE_HIGHADDR Instruction cache high address 0x0 - 0xFFFFFFFF FFFFFFFF 0x3FFFFFFF   std_logic_vector
C_USE_ICACHE Instruction cache 0, 1 0   Integer
C_ICACHE_LINE_LEN Instruction cache line length 4, 8, 16 4   Integer
C_ICACHE_FORCE_TAG_LUTRAM Instruction cache tag always implemented with distributed RAM 0, 1 0   Integer
C_ICACHE_STREAMS Instruction cache streams 0, 1 0   Integer
C_ICACHE_VICTIMS Instruction cache victims 0, 2, 4, 8 0   Integer
C_ICACHE_DATA_WIDTH Instruction cache data width:
  • 0 = 32 bits
  • 1 = Full cache line
  • 2 = 512 bits
 0, 1, 2 0   Integer
C_ICACHE_BYTE_SIZE Instruction cache size 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 2 8192   Integer
C_DCACHE_BASEADDR Data cache base address 0x0 - 0xFFFFFFFF FFFFFFFF 0x0   std_logic_vector
C_DCACHE_HIGHADDR Data cache high address 0x0 - 0xFFFFFFFF FFFFFFFF 0x3FFFFFFF   std_logic_vector
C_USE_DCACHE Data cache 0, 1 0   Integer
C_DCACHE_LINE_LEN Data cache line length 4, 8, 16 4   Integer
C_DCACHE_FORCE_TAG_LUTRAM Data cache tag always implemented with distributed RAM 0, 1 0   Integer
C_DCACHE_USE_WRITEBACK Data cache write-back storage policy used 0, 1 0   Integer
C_DCACHE_VICTIMS Data cache victims 0, 2, 4, 8 0   Integer
C_DCACHE_DATA_WIDTH Data cache data width:
  • 0 = 32 bits
  • 1 = Full cache line
  • 2 = 512 bits
 0, 1, 2 0   Integer
C_DCACHE_BYTE_SIZE Data cache size 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 2 8192   Integer
C_USE_MMU Memory management mode:
  • 0 = Machine
  • 1 = User
  • 3 = Supervisor
 0, 1, 3 0   Integer
C_MMU_PRIVILEGED_INSTR Allow user mode access to stream CSR 0, 1 0   Integer
C_USE_INTERRUPT Enable interrupt handling:
  • 0 = No interrupt
  • 1 = Standard
  • 2 = Fast
 0, 1, 2 1 Yes Integer
C_USE_EXT_BRK Enable external break handling (platform interrupt) 0, 1 0   Integer
C_USE_EXT_NM_BRK Enable external non-maskable break (non-maskable interrupt) 0, 1 0   Integer
C_USE_SLEEP Enable sleep, hibernate, suspend outputs:
  • Bit 0 = Sleep
  • Bit 1 = Hibernate
  • Bit 2 = Suspend
 0-7 0   Integer
C_USE_NON_SECURE Use corresponding non-secure input 0-15 0 Yes Integer
C_USE_BRANCH_TARGET_CACHE Enable branch target cache 0,1 0   Integer
C_BRANCH_TARGET_CACHE_SIZE Branch target cache size:
  • 0 = Default (1024 entries)
  • 1 = 8 entries
  • 2 = 16 entries
  • 3 = 32 entries
  • 4 = 64 entries
  • 5 = 512 entries
  • 6 = 1024 entries
  • 7 = 2048 entries
 0-7 0   Integer
C_M_AXI_DP_THREAD_ID_WIDTH Data side AXI thread ID width 1 1   Integer
C_M_AXI_DP_DATA_WIDTH Data side AXI data width 32 32   Integer
C_M_AXI_DP_ADDR_WIDTH Data side AXI address width 32-64 32 Yes Integer
C_M_AXI_DP_SUPPORTS_THREADS Data side AXI uses threads 0 0   Integer
C_M_AXI_DP_SUPPORTS_READ Data side AXI support for read accesses 1 1   Integer
C_M_AXI_DP_SUPPORTS_WRITE Data side AXI support for write accesses 1 1   Integer
C_M_AXI_DP_SUPPORTS_NARROW_BURST Data side AXI narrow burst support 0 0   Integer
C_M_AXI_DP_PROTOCOL Data side AXI protocol AXI4, AXI4LITE AXI4 LITE Yes String
C_M_AXI_DP_EXCLUSIVE_ACCESS Data side AXI exclusive access support 0,1 0   Integer
C_M_AXI_IP_THREAD_ID_WIDTH Instruction side AXI thread ID width 1 1   Integer
C_M_AXI_IP_DATA_WIDTH Instruction side AXI data width 32 32   Integer
C_M_AXI_IP_ADDR_WIDTH Instruction side AXI address width 32-64 32 Yes Integer
C_M_AXI_IP_SUPPORTS_THREADS Instruction side AXI uses threads 0 0   Integer
C_M_AXI_IP_SUPPORTS_READ Instruction side AXI support for read accesses 1 1   Integer
C_M_AXI_IP_SUPPORTS_WRITE Instruction side AXI support for write accesses 0 0   Integer
C_M_AXI_IP_SUPPORTS_NARROW_BURST Instruction side AXI narrow burst support 0 0   Integer
C_M_AXI_IP_PROTOCOL Instruction side AXI protocol AXI4LITE AXI4 LITE   String
C_M_AXI_DC_THREAD_ID_WIDTH Data cache AXI ID width 1 1   Integer
C_M_AXI_DC_DATA_WIDTH Data cache AXI data width 32, 64, 128, 256, 512 32   Integer
C_M_AXI_DC_ADDR_WIDTH Data cache AXI address width 32-64 32 Yes Integer
C_M_AXI_DC_SUPPORTS_THREADS Data cache AXI uses threads 0 0   Integer
C_M_AXI_DC_SUPPORTS_READ Data cache AXI support for read accesses 1 1   Integer
C_M_AXI_DC_SUPPORTS_WRITE Data cache AXI support for write accesses 1 1   Integer
C_M_AXI_DC_SUPPORTS_ NARROW_BURST Data cache AXI narrow burst support 0 0   Integer
C_M_AXI_DC_SUPPORTS_USER_SIGNALS Data cache AXI user signal support 1 1   Integer
C_M_AXI_DC_PROTOCOL Data cache AXI protocol AXI4 AXI4   String
C_M_AXI_DC_AWUSER_WIDTH Data cache AXI user width 5 5   Integer
C_M_AXI_DC_ARUSER_WIDTH Data cache AXI user width 5 5   Integer
C_M_AXI_DC_WUSER_WIDTH Data cache AXI user width 1 1   Integer
C_M_AXI_DC_RUSER_WIDTH Data cache AXI user width 1 1   Integer
C_M_AXI_DC_BUSER_WIDTH Data cache AXI user width 1 1   Integer
C_M_AXI_DC_EXCLUSIVE_ACCESS Data cache AXI exclusive access support 0,1 0   Integer
C_M_AXI_DC_USER_VALUE Data cache AXI user value 0-31 31   Integer
C_M_AXI_IC_THREAD_ID_WIDTH Instruction cache AXI ID width 1 1   Integer
C_M_AXI_IC_DATA_WIDTH Instruction cache AXI data width 32, 64, 128, 256, 512 32   Integer
C_M_AXI_IC_ADDR_WIDTH Instruction cache AXI address width 32-64 32 Yes Integer
C_M_AXI_IC_SUPPORTS_THREADS Instruction cache AXI uses threads 0 0   Integer
C_M_AXI_IC_SUPPORTS_READ Instruction cache AXI support for read accesses 1 1   Integer
C_M_AXI_IC_SUPPORTS_WRITE Instruction cache AXI support for write accesses 0 0   Integer
C_M_AXI_IC_SUPPORTS_NARROW_BURST Instruction cache AXI narrow burst support 0 0   Integer
C_M_AXI_IC_SUPPORTS_ USER_SIGNALS Instruction cache AXI user signal support 1 1   Integer
C_M_AXI_IC_PROTOCOL Instruction cache AXI protocol AXI4 AXI4   String
C_M_AXI_IC_AWUSER_WIDTH Instruction cache AXI user width 5 5   Integer
C_M_AXI_IC_ARUSER_WIDTH Instruction cache AXI user width 5 5   Integer
C_M_AXI_IC_WUSER_WIDTH Instruction cache AXI user width 1 1   Integer
C_M_AXI_IC_RUSER_WIDTH Instruction cache AXI user width 1 1   Integer
C_M_AXI_IC_BUSER_WIDTH Instruction cache AXI user width 1 1   Integer
C_M_AXI_IC_USER_VALUE Instruction cache AXI user value 0-31 31   Integer
C_Mn_AXIS_PROTOCOL AXI4-Stream protocol Generic Generic   Integer
C_Sn_AXIS_PROTOCOL AXI4-Stream protocol Generic Generic   Integer
C_Mn_AXIS_DATA_WIDTH AXI4-Stream master data width 32 32 NA Integer
C_Sn_AXIS_DATA_WIDTH AXI4-Stream slave data width 32 32 NA Integer
C_NUM_SYNC_FF_CLK Reset and Wakeup[0:1] synchronization stages ≥0 2   Integer
C_NUM_SYNC_FF_CLK_IRQ Interrupt input signal synchronization stages ≥0 1   Integer
C_NUM_SYNC_FF_CLK_DEBUG Debug serial signal synchronization stages ≥0 2   Integer
C_NUM_SYNC_FF_DBG_CLK Internal synchronization stages to Dbg_Clk ≥0 1   Integer
  1. The 7 least significant bits must all be 0.
  2. Not all sizes are permitted in all architectures. The cache uses 0–32 RAMB primitives (0 if cache size is less than 2048).
Table 2. Parameter C_FAMILY Allowable Values
Device Family Allowable Values
Artix devices aartix7 artix7 artix7l qartix7 qartix7l artixuplus
Kintex 7, Kintex UltraScale, Kintex UltraScale+ devices kintex7 kintex7l qkintex7 qkintex7l kintexu kintexuplus
Spartan devices spartan7
Virtex 7, Virtex UltraScale, Virtex UltraScale+ devices qvirtex7 virtex7 virtexu virtexuplus virtexuplusHBM
Zynq devices azynq zynq qzynq zynquplus zynquplusRFSOC
Versal devices versal

The following table lists the parameters associated with each configurable feature.

Table 3. Configurable Feature Parameters
Feature Associated Parameter
Processor pipeline depth C_OPTIMIZATION
"M" Standard Extension for Integer Multiplier and Divider C_USE_MULDIV
"A" Standard Extension for Atomic Instructions C_USE_ATOMIC
"C" Standard Extension for Compressed Instructions C_USE_COMPRESSION
"F" Standard Extension for Single-Precision Floating-Point C_USE_FPU = 1
"Zba", "Zbb", "Zbc", "Zbs" Bit-Manipulation ISA Extensions C_USE_ZBA, C_USE_ZBB, C_USE_ZBC, C_USE_ZBS
User-mode C_USE_MMU = 1
Physical Memory Protection C_PMP_ENTRIES > 0
Supervisor Level ISA C_USE_MMU = 3
Page-Based Virtual Memory System C_USE_MMU = 3
External debug support C_DEBUG_ENABLED
Parallel debug module interface C_DEBUG_INTERFACE = 1
Branch target cache (BTC) C_USE_BRANCH_TARGET_CACHE
Local memory bus (LMB) data side interface C_D_LMB
Local memory bus (LMB) instruction side interface C_I_LMB
Instruction and data caches C_USE_ICACHE, C_USE_DCACHE
Cache line word length C_ICACHE_LINE_LEN, C_DCACHE_LINE_LEN
LUT cache memory C_ICACHE_BYTE_SIZE ≤ 1024, C_DCACHE_BYTE_SIZE ≤ 1024
Use write-back caching policy for D-Cache C_DCACHE_USE_WRITEBACK
Streams for I-Cache C_ICACHE_STREAMS
Victim handling for I-Cache C_ICACHE_VICTIMS
Victim handling for D-Cache C_DCACHE_VICTIMS
Force distributed RAM for cache tags C_ICACHE_FORCE_TAG_LUTRAM, C_DCACHE_FORCE_TAG_LUTRAM
Configurable cache data widths C_ICACHE_DATA_WIDTH, C_DCACHE_DATA_WIDTH
AXI4 (M_AXI_DP) data side interface C_D_AXI
AXI4 (M_AXI_IP) instruction side interface C_I_AXI
AXI4 (M_AXI_DC) protocol for D-Cache C_INTERCONNECT = 2
AXI4 (M_AXI_IC) protocol for I-Cache C_INTERCONNECT = 2
ACE (M_ACE_DC) protocol for D-Cache C_INTERCONNECT = 3
ACE (M_ACE_IC) protocol for I-Cache C_INTERCONNECT = 3
AXI4 non-secure mode C_USE_NON_SECURE
Lockstep support C_LOCKSTEP_SLAVE
Configurable use of FPGA primitives C_AVOID_PRIMITIVES
Relocatable base vectors C_BASE_VECTORS
Pipeline pause functionality C_ENABLE_DISCRETE_PORTS

The following table lists the parameters associated with each MicroBlaze V external interface.

Table 4. Interface Parameters
Interface Associated Parameter
M_AXI_DP C_D_AXI
DLMB C_D_LMB
M_AXI_IP C_I_AXI
ILMB C_I_LMB
M0_AXIS..M15_AXIS, S0_AXIS..S15_AXIS C_FSL_LINKS
M_AXI_DC C_USE_DCACHE, C_INTERCONNECT = 2
M_ACE_DC C_USE_DCACHE, C_INTERCONNECT = 3
M_AXI_IC C_USE_ICACHE, C_INTERCONNECT = 2
M_ACE_IC C_USE_ICACHE, C_INTERCONNECT = 3
INTERRUPT C_USE_INTERRUPT
DEBUG C_DEBUG_ENABLED