Machine Status Register (mstatus) - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)

Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

The mstatus register is a read/write register formatted as shown in the following figures for RV32 and RV64. The mstatus register keeps track of and controls the current operating state of the hart.

Figure 1. Machine Status Register Formatted for RV32

Figure 2. Machine Status Register Formatted for RV64

Table 1. Machine Status Register
Bits Name Description Reset Value
63,31 SD

The SD bit is a read-only bit that indicates whether the FS field signals the presence of some dirty state that requires saving extended floating-point context to memory.

Exists if floating-point is implemented (C_USE_FPU > 0), read-only 0 otherwise.

0: FS ≠ 11

1: FS = 11

35:34 SXL The SXL field is a read-only field only available for RV64 that indicates that supervisor mode XLEN is 64 bits.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 00 otherwise.

10
33:32 UXL The UXL field is a read-only field only available for RV64 that indicates that user mode XLEN is 64 bits.

Exists if user mode is implemented (C_USE_MMU > 0), read-only 00 otherwise.

10
22 TSR

Trap SRET. When TSR = 1, if SRET is executed in supervisor mode, the instruction causes an illegal instruction exception.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 0 otherwise.
0
21 TW

When TW=0, the WFI instruction might execute in user mode. When TW=1, if WFI is executed in user mode, the instruction causes an illegal instruction exception.

Exists if user mode is implemented (C_USE_MMU > 0), read-only 0 otherwise.

0
20 TVM

Trap virtual memory. When TVM = 1, if SFENCE.VMA is executed or SATP is accessed in supervisor mode, an illegal instruction exception occurs.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 0 otherwise.
0
19 MXR

Make eXecutable readable.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 0 otherwise.
0
18 SUM

Permit supervisor user Memory access.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 0 otherwise.
0
17 MPRV The MPRV (modify privilege) bit modifies the effective privilege mode.

Exists if user mode is implemented (C_USE_MMU > 0), read-only 0 otherwise.

0
14:13 FS FS tracks the current state of the floating-point unit.

Exists if floating-point is implemented (C_USE_FPU > 0), read-only 00 otherwise.

00: C_USE_FPU = 0

01: C_USE_FPU > 0

12:11 MPP

Machine previous privilege mode.

Exists if user mode is implemented (C_USE_MMU > 0), read-only 11 otherwise.
11: C_USE_MMU = 0

00: C_USE_MMU > 0

8 SPP

Supervisor previous privilege mode.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 0 otherwise.
0
7 MPIE Previous MIE. 0
5 SPIE Previous SIE.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 0 otherwise.

0
3 MIE Global interrupt enable for machine mode. 0
1 SIE Global interrupt enable for supervisor mode.

Exists if supervisor mode is implemented (C_USE_MMU > 2), read-only 0 otherwise.

0