Machine Interrupt Registers (mip and mie) - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

The mip register is a read-only register containing information on pending interrupts, while mie is the corresponding read/write register containing interrupt enable bits.

Figure 1. Machine Interrupt Break Pending (MEBP) and Machine External Interrupt Pending (MEIP)

Table 1. Machine Interrupt Pending Register
Bits Name Description Reset Value
16 MEBP Machine external break pending. Custom platform interrupt, using the external break input. Ext_Brk
11 MEIP Machine external interrupt pending. Interrupt
Figure 2. Machine External Break Enable (MEBE) and Machine External Interrupt Enable (MEIE)

Table 2. Machine Interrupt Enable Register
Bits Name Description Reset Value
16 MEBE Machine external break enable. Custom platform interrupt, using the external break input. 0
11 MEIE Machine external interrupt enable. 0