Machine Cause Register (mcause) - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

The mcause register is a read/write register. When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap.

The code uses four bits, unless extended AXI4-Stream custom instructions with exception support are enabled (C_FSL_LINKS > 0, C_EXTENDED_FSL_INSTR > 0, and C_FSL_EXCEPTION > 0), in which case it uses five bits.

Figure 1. Machine Cause Register

Table 1. Machine Cause Register
Bits Name Description Reset Value
31 Interrupt Set if the trap was caused by an interrupt 0
4:0, 3:0 Code Contains a code identifying the last exception or interrupt 00000, 0000

The processor supports the following interrupt and exception codes:

Table 2. Interrupt and Exception Codes
Interrupt Code Description
1 0 Non-maskable interrupt. Occurs when the Ext_NM_BRK signal is pulsed.

Exists when C_USE_EXT_NM_BRK > 0.
1 11 Machine external interrupt. Occurs when the Interrupt signal is activated.

Exists when C_USE_INTERRUPT > 0.
1 16 Machine external break platform interrupt. Occurs when the Ext_BRK signal is set.

Exists when C_USE_EXT_BRK > 0.
0 0 Instruction address misaligned.

Exists when compressed instructions are not enabled (C_USE_COMPRESSION = 0).
0 1 Instruction access fault.
  • Caused by a bus error, either from an LMB uncorrectable error, an LMB correctable error when C_USE_ECC_CE_EXCEPTION > 0, an AXI4 slave error, or an AXI4 decode error.
  • Caused by an AXI4 OKAY response to a load-reserved (LR) or atomic (AMO) instruction load when exclusive accesses are enabled on the AXI4 interface.
  • Caused by a physical memory protection (PMP) check when PMP is enabled (C_PMP_ENTRIES > 0).

Exists when C_M_AXI_I_BUS_EXCEPTION > 0 or C_PMP_ENTRIES > 0.
0 2 Illegal instruction.

Exists when illegal instruction exceptions are enabled (C_ILL_INSTR_EXCEPTION > 0).
0 3 Breakpoint (EBREAK)

Exists when debug is enabled (C_DEBUG_ENABLED > 0).
0 4 Load address misaligned
0 5 Load access fault.
  • Caused by a bus error, either from an LMB uncorrectable error, an LMB correctable error when C_USE_ECC_CE_EXCEPTION > 0, an AXI4 slave error, or an AXI4 decode error. A bus error can also occur during virtual memory translation page table lookup.
  • Caused by a physical memory protection (PMP) check when PMP is enabled (C_PMP_ENTRIES > 0).

Exists when C_M_AXI_D_BUS_EXCEPTION > 0, C_PMP_ENTRIES > 0, or when supervisor mode is enabled (C_USE_MMU > 1).
0 6 Store/AMO address misaligned
0 7 Store/AMO access fault.
  • Caused by a bus error, either from an LMB uncorrectable error, an LMB correctable error when C_USE_ECC_CE_EXCEPTION > 0, an AXI4 slave error, or an AXI4 decode error.
  • Caused by a physical memory protection (PMP) check when PMP is enabled (C_PMP_ENTRIES > 0).

Exists when C_M_AXI_D_BUS_EXCEPTION > 0 or C_PMP_ENTRIES > 0.
0 8 Environment call from U-mode (ECALL).

Exists when user mode is enabled (C_USE_MMU > 0).
0 9 Environment call from S-mode (ECALL).

Exists when supervisor mode is enabled (C_USE_MMU > 1).
0 11 Environment call from M-mode (ECALL)
0 12 Instruction page fault.

Exists when supervisor mode is enabled (C_USE_MMU > 1).
0 13 Load page fault.

Exists when supervisor mode is enabled (C_USE_MMU > 1).
0 15 Store/AMO page fault.

Exists when supervisor mode is enabled (C_USE_MMU > 1).
0 24 AXI4-Stream exception.

Exists when extended AXI4-Stream custom instructions with exception support are enabled (C_FSL_LINKS > 0, C_EXTENDED_FSL_INSTR > 0, and C_FSL_EXCEPTION > 0.