| Signal | Data Interface | Instruction Interface | Type | Description |
|---|---|---|---|---|
| Addr[0:N-1] 1 | Data_Addr[0:N-1] | Instr_Addr[0:N-1 | O | Address bus |
| Byte_Enable[0:3] | Byte_Enable[0:3] | Not used | O | Byte enables |
| Data_Write[0:31] | Data_Write[0:31] | Not used | O | Write data bus |
| AS | D_AS | I_AS | O | Address strobe |
| Read_Strobe | Read_Strobe | IFetch | O | Read in progress |
| Write_Strobe | Write_Strobe | Not used | O | Write in progress |
| Data_Read[0:31] | Data_Read[0:31] | Instr[0:31] | I | Read data bus |
| Ready | DReady | IReady | I | Ready for next transfer |
| Wait | DWait | IWait | I | Wait until accepted transfer is ready |
| CE | DCE | ICE | I | Correctable error |
| UE | DUE | IUE | I | Uncorrectable error |
| Clk | Clk | Clk | I | Bus clock |
|
||||
Address
The address bus is an output from the core and indicates the memory address
that is being accessed by the current transfer. It is valid only when AS is High. In
multicycle accesses requiring more than one clock cycle to complete, Addr[0:N-1] is valid only in the first clock cycle of
the transfer.
Byte Enables
The byte enable signals are outputs from the core and indicate which byte
lanes of the data bus contain valid data. Byte_Enable[0:3] is valid only when AS is High. In multicycle accesses
requiring more than one clock cycle to complete, Byte_Enable[0:3] is valid only in the first clock cycle of the
transfer. Valid values for Byte_Enable[0:3] are
shown in the following table.
| Byte Enable | Byte Lanes Used | |||
|---|---|---|---|---|
| Data[0:7] | Data[8:15] | Data[16:23] | Data[24:31] | |
| 0001 | ● | |||
| 0010 | ● | |||
| 0100 | ● | |||
| 1000 | ● | |||
| 0011 | ● | ● | ||
| 1100 | ● | ● | ||
| 1111 | ● | ● | ● | ● |
Data Write
The write data bus is an output from the core and contains the data that is
written to memory. It is valid only when AS is High. Only the byte lanes specified
by Byte_Enable[0:3] contain valid data.
Address Strobe
The address strobe is an output from the core and indicates the start of a transfer and qualifies the address bus and the byte enables. It is High only in the first clock cycle of the transfer, after which it goes Low and remains Low until the start of the next transfer.
Read Strobe
The read strobe is an output from the core and indicates that a read transfer
is in progress. This signal goes High in the first clock cycle of the transfer, and
can remain High until the clock cycle after Ready
is sampled High. If a new read transfer is directly started in the next clock cycle,
Read_Strobe remains High. The read strobe is
never High at the same time as the write strobe.
Write Strobe
The write strobe is an output from the core and indicates that a write
transfer is in progress. This signal goes High in the first clock cycle of the
transfer, and can remain High until the clock cycle after Ready is sampled High. If a new write transfer is directly started in
the next clock cycle, Write_Strobe remains High.
The write strobe is never High at the same time as the read strobe.
Data Read
The read data bus is an input to the core and contains data read from memory.
Data_Read is valid on the rising edge of the
clock when Ready is High.
Ready
The Ready signal is an input to the core and indicates
completion of the current transfer and that the next transfer can begin in this
clock cycle. It is sampled on the rising edge of the clock. For reads, this signal
indicates the Data_Read[0:31] bus is valid, and
for writes it indicates that the Data_Write[0:31]
bus has been written to local memory.
Wait
The Wait signal is an input to the core and indicates that
the current transfer has been accepted, but not yet completed. It is sampled on the
rising edge of the clock. The Wait signal is ignored when
Ready is High.
CE
The CE signal is an input to the core and
indicates that the current transfer had a correctable error. It is valid on the
rising edge of the clock when Ready is High. For reads, this signal
indicates that an error has been corrected on the Data_Read[0:31] bus, and for byte and half word writes it indicates
that the corresponding data word in local memory has been corrected before writing
the new data.
UE
The UE signal is an input to the core and
indicates that the current transfer had an uncorrectable error. It is valid on the
rising edge of the clock when Ready is High. For reads, this signal
indicates that the value of the Data_Read[0:31]
bus is erroneous, and for byte and half word writes it indicates that the
corresponding data word in local memory was erroneous before writing the new
data.
Clk
All operations on the LMB are synchronous to the MicroBlaze V clock.