The coherency hardware in the caches handles invalidation in the following
cases:
- Data cache invalidation
- When a MicroBlaze V core in the coherency domain invalidates a data cache line with an external cache invalidation instruction, hardware messages ensure that all other cores in the coherency domain do the same. The physical address is always used.
- Instruction cache invalidation
- When a MicroBlaze V core in the coherency domain invalidates an instruction cache line, hardware messages ensure that all other cores in the coherency domain do the same.
- Branch target cache invalidation
- When a MicroBlaze V core in the coherency domain invalidates the branch target cache, either with a memory barrier instruction or with a synchronizing branch, hardware messages ensure that all other cores in the coherency domain do the same.
In particular, this means that self-modifying code can be used transparently within the coherency domain in a multi-processor system, provided that the guidelines regarding self-modifying code are followed.