Instructions - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)

Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

MicroBlaze V implements instructions as defined by the RISC-V Instruction Set Manual.

Instruction latency is listed in the following table where differences due to pipeline optimization are indicated, as well as optional instructions and their controlling parameters.

Table 1. Instruction Latency
Instruction Mnemonics Latency Remark
RV32I Base Integer Instruction Set    
LUI 1  
AUIPC 1  
JAL, JALR 3 3-, 4-, 5-stage pipeline
5 8-stage pipeline
BEQ, BNE, BLT, BGE, BLTU, BGEU 1 If branch is not taken
3 If branch is taken, 3-, 4-, 5-stage pipeline
5 If branch is taken, 8-stage pipeline
LB, LH, LW, LBU, LHU, SB, SH, SW 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
ADDI, SLTI, SLTIU, XORI, ORI, ANDI 1  
ADD, SUB, SLT, SLTU, XOR, OR, AND 1  
SLLI, SRLI, SRAI, SLL, SRL, SRA 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
FENCE 1 2 + N C_INTERCONNECT = 2 (AXI)
8 + N C_INTERCONNECT = 3 (ACE)
ECALL 5  
EBREAK 5  
RV64I Base Integer Instruction Set   C_DATA_SIZE = 64
ADDIW 1  
ADDW, SUBW 1  
SLLIW, SRLIW, SRAIW, SLLW, SRLW, SRAW 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
LWU 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
LD, SD 2 1, 2 4-, 5-, 8-stage pipeline
2, 3 3-stage pipeline
RV32/RV64 Zifencei Standard Extension  
FENCE.I 1 2 + N C_INTERCONNECT = 2 (AXI)
8 + N C_INTERCONNECT = 3 (ACE)
RV32/RV64 Zicsr Standard Extension
CSRRW, CSRRS, CSRRC 1  
CSRRWI, CSRRSI, CSRRCI 1  
RV32M Standard Extension C_USE_MULDIV > 0, C_DATA_SIZE = 32
MUL, MULH, MULHSU, MULHU 1 4-, 5-, 8-stage pipeline
3 3-stage pipeline
DIV, DIVU 3 30 8-stage pipeline
34 5-stage pipeline
35 3-, 4-stage pipeline
REM, REMU 3 31 8-stage pipeline
35 5-stage pipeline
36 3-, 4-stage pipeline
RV32M Standard Extension C_USE_MULDIV > 0, C_DATA_SIZE = 64
MUL, MULH, MULHSU, MULHU 2 4-, 5-, 8-stage pipeline
4 3-stage pipeline
DIV, DIVU 3 62 8-stage pipeline
66 5-stage pipeline
67 3-, 4-stage pipeline
REM, REMU 3 63 8-stage pipeline
67 5-stage pipeline
68 3-, 4-stage pipeline
RV64M Standard Extension C_DATA_SIZE = 64
MULW 1 4-, 5-, 8-stage pipeline
3 3-stage pipeline
DIVW, DIVUW 3 30 8-stage pipeline
34 5-stage pipeline
35 3-, 4-stage pipeline
REMW, REMUW 3 31 8-stage pipeline
35 5-stage pipeline
36 3-, 4-stage pipeline
RV32A Standard Extension C_USE_ATOMIC = 1
LR.W 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
SC.W 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
AMO*.W 5 4-, 5-, 8-stage pipeline
7 3-stage pipeline
RV64A Standard Extension 2 C_USE_ATOMIC = 1, C_DATA_SIZE = 64
LR.D 1, 2 4-, 5-, 8-stage pipeline
2, 3 3-stage pipeline
SC.D 1, 2 4-, 5-, 8-stage pipeline
2, 3 3-stage pipeline
AMO*.D 5, 6 4-, 5-, 8-stage pipeline
7, 8 3-stage pipeline
RV32F Standard Extension 4 C_USE_FPU = 1
FLW, FSW 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
FMADD.S, FMSUB.S, FNMADD.S, FNMSUB.S 2 8-stage pipeline
5 5-stage pipeline
6 4-stage pipeline
7 3-stage pipeline
FADD.S, FSUB.S 1 8-stage pipeline
4 5-stage pipeline
5 4-stage pipeline
6 3-stage pipeline
FMUL.S 1 8-stage pipeline
3 5-stage pipeline
4 4-stage pipeline
5 3-stage pipeline
FDIV.S 26 8-stage pipeline
30 4-, 5-stage pipeline
32 3-stage pipeline
FSQRT.S 25 8-stage pipeline
29 4-, 5-stage pipeline
31 3-stage pipeline
FSGNJ.S, FSGNJN.S, FSGNJX.S, FMIN.S, FMAX.S, FCLASS.S 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
FCVT.W.S, FCVT.WU.S 1 8-stage pipeline
4 5-stage pipeline
5 4-stage pipeline
6 3-stage pipeline
FEQ.S, FLT.S, FLE.S 1 4-, 5-, 8-stage pipeline
3 3-stage pipeline
FCVT.S.W, FCVT.S.WU 1 8-stage pipeline
4 5-stage pipeline
5 4-stage pipeline
6 3-stage pipeline
FMV.X.W, FMV.W.X 1  
RV64F Standard Extension C_USE_FPU = 1, C_DATA_SIZE = 64
FCVT.L.S, FCVT.LU.S 1 8-stage pipeline
4 5-stage pipeline
5 4-stage pipeline
6 3-stage pipeline
FCVT.S.L, FCVT.S.LU 1 8-stage pipeline
4 5-stage pipeline
5 4-stage pipeline
6 3-stage pipeline
Zba Extension C_USE_BITMAN_A = 1
ADD.UW, SH1ADD, SH1ADD.UW, SH2ADD, SH2ADD.UW, SH3ADD, SH3ADD.UW, SLLI.UW 1  
Zbb Extension C_USE_BITMAN_B = 1
ANDN, CLZ, CLZW, CPOP, CPOPW, CTZ, CTZW, ORC.B, ORN, REV8, ROL, ROLW, ROR, RORL, RORIW, RORW 1  
MAX, MAXU, MIN, MINU 1 4-, 5-, 8-stage pipeline
2 3-stage pipeline
SEXT.B, SEXT.H, XNOR, ZEXT.H 1  
Zbc Extension C_USE_BITMAN_C = 1
CLMUL, CLMULH, CLMULR 32  
Zbs Extension C_USE_BITMAN_S = 1
BCLR, BCLRI, BEXT, BEXTI, BINV, BINVI, BSET, BSETI 1  
Zicbom Extension C_USE_ICACHE = 1 or C_USE_DCACHE = 1
CBO.INVAL, CBO.CLEAN, CBO.FLUSH 1 2 + N C_INTERCONNECT = 2 (AXI)
8 + N C_INTERCONNECT = 3 (ACE)
  1. N is the number of cycles to wait for memory accesses to complete.
  2. Latency depends on the accessed memory interface width.
  3. Latency is 1 when the denominator is 0. When C_USE_MULDIV = 2, division and remainder are optimized to reduce the latency for byte operands with 24 cycles and for short operands with 16 cycles. For RV64, the optimization is only applied if the 32 most significant bits are zero.
  4. If any of the operands is a subnormal floating-point value, the latency is increased by one cycle.