The MicroBlaze V processor can be used with an optional instruction cache for improved performance when executing code that resides outside the LMB address range.
The instruction cache has the following features:
- Direct mapped (one-way associative)
- Cleared by hardware after reset
- Cleared by the FENCE.I instruction
- User selectable cacheable memory address range
- Configurable cache and tag size
- Caching over AXI4 interface (M_AXI_IC)
- Option to use 4, 8, or 16 word cache-line
- Optional stream buffers to improve performance by speculatively prefetching instructions
- Optional victim cache to improve performance by saving evicted cache lines
- Optional parity protection that invalidates cache lines if a block RAM bit error is detected
- Optional data width selection to either use 32 bits, an entire cache line, or 512 bits