When the data cache is used, the memory address space is split into two
segments: a cacheable segment and a non-cacheable segment. The cacheable area is
determined by two parameters: C_DCACHE_BASEADDR and
C_DCACHE_HIGHADDR. All addresses within this range
correspond to the cacheable address space. All other addresses are non-cacheable.
The cacheable segment size must be 2N, where N is a
positive integer. The range specified by C_DCACHE_BASEADDR and C_DCACHE_HIGHADDR
must comprise a complete power-of-two range, such that range = 2N and the N
least significant bits of C_DCACHE_BASEADDR must be
zero.
The following figure shows the data cache organization.
The cacheable data address consists of two parts: the cache address, and the
tag address. The data cache can be configured from 64 bytes to 64 kB. This corresponds
to a cache address of between 6 and 16 bits. The tag address together with the cache
address should match the full address of cacheable memory. When selecting cache sizes
below 2 kB, distributed RAM is used to implement the tag RAM and data RAM. Distributed
RAM is always used to implement the tag RAM, when setting the parameter C_DCACHE_FORCE_TAG_LUTRAM to 1. This parameter is only
available with cache size 8 kB and less for 4 word cache-lines, with 16 kB and less for
8 word cache-lines, and with 32 kB and less for 16 word cache-lines.
For example, in a 32-bit MicroBlaze V configured
with C_DCACHE_BASEADDR= 0x0040_0000, C_DCACHE_HIGHADDR= 0x0040_3fff, C_DCACHE_BYTE_SIZE= 2048, C_DCACHE_LINE_LEN= 4, and C_DCACHE_FORCE_TAG_LUTRAM= 0; the cacheable memory of 16 kB uses 14 bits
of byte address, and the 2 kB cache uses 11 bits of byte address, thus the required
address tag width is 14-11=3 bits. The total number of block RAM primitives required in
this configuration is 1 RAMB16 for storing the 512 data words, and 1 RAMB16 for 128
cache line entries, each consisting of 3 bits of tag, 4 word-valid bits, 1 line-valid
bit. The total is 2 RAMB16 primitives.