GETD - 2024.1 English - UG1629

Description

MicroBlaze V reads from the link defined by the four least significant bits in rs2 and places the result in register rD. If the available number of links set by C_FSL_LINKS is less than or equal to the four least significant bits in rs2, link 0 is used.

The GETD instruction has 32 variants.

The blocking versions (when the n bit is 0) stall until the data from the interface is valid. The non-blocking versions do not stall, and set the C bit in mstream to 0 if the data is valid and to 1 if the data is invalid. In case of an invalid access, the destination register contents are undefined.

All data GETD instructions (when the c bit is 0) expect the control bit from the interface to be 0. If this is not the case, the instruction sets the FSL bit in mstream to 1. All control GETD instructions (when the c bit is 1) expect the control bit from the interface to be 1. If this is not the case, the instruction sets the FSL bit in mstream to 1.

The exception versions (when the e bit is 1) generate an exception if there is a control bit mismatch. The destination register is not updated when an exception is generated.

The test versions (when the t bit is 1) are handled as normal, except that the read signal to the link is not asserted.

The atomic versions (when the a bit is 1) cannot be interrupted by a machine external interrupt or external break. Each atomic instruction prevents the subsequent instruction from being interrupted. This means that a sequence of atomic instructions can be grouped together without an interrupt breaking the program flow. However, exceptions might still occur.

Pseudocode

x ← rs2[3:0]
if x >= C_FSL_LINKS then
	x ← 0
(rD) ← Sx_AXIS_TDATA
if n = 1 then
   mstream.C ← Sx_AXIS_TVALID
if Sx_AXIS_TLAST ≠ c and Sx_AXIS_TVALID then
   mstream.FSL ← 1
   if (e = 1) then
      PC ← mtval
      mcause ← 24

Registers Altered

• xd, unless an exception is generated, in which case the register is unchanged.
• mstream
• PC and mcause, in case a stream exception is generated.

Latency

• One cycle with C_OPTIMIZATION = 0, 2, 3
• Two cycles with C_OPTIMIZATION = 1

The blocking versions of this instruction stall the pipeline until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.

Notes

• The e bit does not have any effect unless C_FSL_EXCEPTION is set to 1.
• These instructions are only available when the parameter C_FSL_LINKS is greater than 0.
• The extended instructions (exception, test, and atomic versions) are only available when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1.