It is important to determine the IP performance in the context of a user system. In the case of the MicroBlaze V characterization, the system includes the following items:
- The IP under test (MicroBlaze V processor)
- Local memory (LMB)
- One level of interconnect (AXI4, AXI4-Lite)
- Memory controller (EMC)
- On-chip block RAM controller
- Peripherals (UART, Timer, Interrupt Controller, MDM V)
Determining the FMAX of an Embedded IP with these components provides a more realistic performance target.
The system above has two types of AXI Interconnect. AXI4-Lite used for peripheral command and control, and AXI4 used for memory accesses.
For FMAX Margin System Analysis, the clock frequency of the system is incremented up to the maximum frequency where the system breaks with timing violations (worst case negative slack). The reported frequency is the failing frequency subtracted with this worst case negative slack.