MicroBlaze V features a debug interface to support software debugging tools (commonly known as background debug mode (BDM) debuggers) such as the AMD Vitis™ System Debugger tool.
The debug interface is designed to be connected to the MicroBlaze Debug Module (MDM) V core, which interfaces with the JTAG port of AMD Adaptive Computing FPGAs or with a memory-mapped AXI4-Lite interface.
The debug functionality is implemented according to the definition in RISC-V External Debug Support, Version 1.0.0-rc2, and is compatible with any third-party tools following this standard.
Multiple MicroBlaze V processors can be interfaced with a single MDM V core to enable multiprocessor debugging. Each processor represents a single RISC-V hardware thread (hart).
To download programs, set software breakpoints and disassemble code, ensure that the instruction and data memory ranges overlap, and use the same physical memory.
Debug registers are accessed using the debug interface, and are not directly
visible to software running on the processor. The debug interface can either use JTAG
serial access or AXI4-Lite parallel access, controlled by the parameter
C_DEBUG_INTERFACE.
See the MicroBlaze Debug Module (MDM) V LogiCORE IP Product Guide (PG428) for a detailed description of the MDM V features.
The debugging features enabled by setting C_DEBUG_ENABLED to 1 include:
- A configurable number of hardware triggers and unlimited software breakpoints
- External control that enables debug tools to stop, reset, and single step the processor
- Ability to read from and write to: memory, general purpose registers, floating-point registers, and control and status registers
- Support for multiple processors (RISC-V harts)