Debug Interface Description - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

The debug interface on MicroBlaze V is designed to work with the MicroBlaze Debug Module (MDM) V IP core. The MDM V is controlled by the Xilinx System Debugger (XSDB) through the JTAG port of the FPGA. The MDM V can control multiple MicroBlaze V processors at the same time. The debug signals are grouped in the DEBUG bus.

The debug interface can be grouped in the DEBUG bus, using either JTAG serial signals (by setting C_DEBUG_INTERFACE = 0) or the AXI4-Lite compatible parallel signals (by setting C_DEBUG_INTERFACE = 1). The MDM V configuration must also be set accordingly.

It is also possible to use only AXI4-Lite parallel signals (C_DEBUG_INTERFACE = 2) grouped in an AXI4 bus, in case the MDM V is not used. However, this configuration is not supported by the tools.

The following table lists the debug signals on MicroBlaze V.

Table 1. MicroBlaze V Debug Signals
Signal Name Description VHDL Type Kind
Dbg_Clk JTAG clock from MDM V std_logic Serial in
Dbg_TDI JTAG TDI from MDM V std_logic Serial in
Dbg_TDO JTAG TDO to MDM V std_logic Serial out
Dbg_Reg_En Debug register enable from MDM V std_logic_vector Serial in
Dbg_Shift JTAG BSCAN shift signal from MDM V std_logic Serial in
Dbg_Capture JTAG BSCAN capture signal from MDM V std_logic Serial in
Dbg_Update JTAG BSCAN update signal from MDM V std_logic Serial in
Debug_Rst Reset signal from MDM V, active-High. Should be held for at least one clk clock cycle. std_logic Input
Dbg_Trig_In Cross trigger event input to MDM V std_logic_vector Output
Dbg_Trig_Ack_In Cross trigger event input acknowledge from MDM V std_logic_vector input
Dbg_Trig_Out Cross trigger action output from MDM V std_logic_vector Input
Dbg_Trig_Ack_Out Cross trigger action output acknowledge to MDM V std_logic_vector Output
Dbg_ARADDR Read address from MDM V std_logic_vector Parallel in
Dbg_ARREADY Read address ready to MDM V std_logic Parallel out
Dbg_ARVALID Read address valid from MDM V std_logic Parallel in
Dbg_AWADDR Write address from MDM V std_logic_vector Parallel in
Dbg_AWREADY Write address ready to MDM V std_logic Parallel out
Dbg_AWVALID Write address valid from MDM V std_logic Parallel in
Dbg_BREADY Write response ready to MDM V std_logic Parallel out
Dbg_BRESP Write response to MDM V std_logic_vector Parallel out
Dbg_BVALID Write response valid from MDM V std_logic Parallel in
Dbg_RDATA Read data to MDM V std_logic_vector Parallel out
Dbg_RREADY Read data ready to MDM V std_logic Parallel out
Dbg_RRESP Read data response to MDM V std_logic_vector Parallel out
Dbg_RVALID Read data valid from MDM V std_logic Parallel in
Dbg_WDATA Write data from MDM V std_logic_vector Parallel in
Dbg_WREADY Write data ready to MDM V std_logic Parallel out
Dbg_WVALID Write data valid from MDM V std_logic Parallel in
DEBUG_ACLK Debug clock, must be same as Clk std_logic Parallel in
DEBUG_ARESET Debug reset, must be same as Reset std_logic Parallel in