The MicroBlaze V processor can be used with an optional data cache for improved performance. The cached memory range must not include addresses in the LMB address range. The data cache has the following features:
- Direct mapped (one-way associative)
- Cleared by hardware after reset
- Cleared by the FENCE.I instruction
- Write-through or write-back
- User selectable cacheable memory address range
- Configurable cache size and tag size
- Caching over AXI4 interface (M_AXI_DC)
- Option to use 4, 8, or 16 word cache lines
- Optional victim cache with write-back to improve performance by saving clean copies of evicted cache lines
- Optional parity protection for write-through cache that invalidates cache lines if a block RAM bit error is detected
- Optional data width selection to either use 32 bits, an entire cache line, or 512 bits