Cache Interfaces - 2024.1 English - UG1629

The AXI4 cache interfaces are implemented either as 32-bit, 128-bit, 256-bit, or 512-bit masters, depending on cache line length and data width parameters, whereas the AXI Coherency Extension (ACE) interfaces are implemented as 32-bit masters.

• With a 32-bit master, the instruction cache interface (M_AXI_IC or M_ACE_IC) performs 4 word, 8 word, or 16 word burst read accesses, depending on cache line length. With 128-bit, 256-bit, or 512-bit masters, only single read accesses are performed.

  With a 32-bit master, this interface can have multiple outstanding transactions, issuing up to two transactions or up to five transactions when stream cache is enabled. The stream cache can request two cache lines in advance, which means that in some cases five outstanding transactions can occur. In this case the number of outstanding reads is set to 8, because this must be a power of two. With 128-bit, 256-bit, or 512-bit masters, the interface only has a single outstanding transaction.

  The cached memory range is always accessed using the AXI4 or ACE cache interface.

• With a 32-bit master, the data cache interface (M_AXI_DC or M_ACE_DC) performs single word accesses, as well as 4 word, 8 word, or 16 word burst accesses, depending on cache line length. Burst write accesses are only performed when using write-back cache with AXI4. With 128-bit, 256-bit, or 512-bit AXI4 masters, only single accesses are performed.

  This interface can have multiple outstanding transactions, either issuing up to two transactions when reading, or up to 32 transactions when writing. MicroBlaze V ensures that all outstanding writes are completed before a read is issued, because the processor must maintain an ordered memory model. However, AXI4 or ACE has separate read/write channels without any ordering. Using up to 32 outstanding write transactions improves performance, because it allows multiple writes to proceed without stalling the pipeline.

  Word, half word and byte writes are performed by setting the appropriate byte strobes.

  Exclusive accesses can be enabled for lr and sc instructions.

  The cached memory range is always accessed using the AXI4 or ACE cache interface.