8-Stage Pipeline - 2024.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)

Document ID
UG1629
Release Date
2024-05-30
Version
2024.1 English

With C_OPTIMIZATION set to 2 (frequency), the pipeline is divided into eight stages to maximize possible frequency: fetch (IF), decode (OF), execute (EX), access memory 0 (M0), access memory 1 (M1), access memory 2 (M2), access memory 3 (M3), and writeback (WB).

Table 1. 8-Stage Pipeline
  Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11  
Instruction 1 IF OF EX M0 M1 M2 M3 WB        
Instruction 2   IF OF EX M0 M0 M1 M3 WB      
Instruction 3     IF OF EX Stall M0 M1 M2 M3 WB  
                         

The 8-stage pipeline has the following kinds of data hazard:

  • An instruction in OF needs the result from an instruction in EX as a source operand. In this case, the EX instruction categories are load, store, multiply, divide, remainder, and floating-point instructions. This results in a 1–5 cycle stall.
  • An instruction in OF uses the result from an instruction in M0 as a source operand. In this case, the M0 instruction categories are load, multiply, divide, remainder, and floating-point instructions. This results in a 1–4 cycle stall.
  • An instruction in OF uses the result from an instruction in M1 or M2 as a source operand. In this case, the M1 or M2 instruction categories are load, divide, remainder, and floating-point instructions. This results in a 1–3 or 1–2 cycle stall respectively.
  • An instruction in OF uses the result from an instruction in M3 as a source operand. In this case, M3 instruction categories are load and floating-point instructions. This results in a 1 cycle stall.

In addition to multi-cycle instructions, there is one other kind of structural hazard: an instruction in M0 is a load or store instruction, and the instruction in M1, M2 or M3 is a load or store instruction that can cause an exception. This results in a 1 cycle stall.

Pipeline stalls are caused by data hazards, control hazards, structural hazards, memory accesses using slower memory, instruction fetch from slower memory, or stream accesses.

The multi-cycle instruction categories are divide and remainder instructions as well as floating-point divide, convert, and square-root instructions.