With C_OPTIMIZATION set to 0 (performance), the pipeline is
divided into five stages to maximize performance: fetch (IF), decode (OF), execute (EX),
access memory (MEM), and writeback (WB).
| Cycle 1 | Cycle 2 | Cycle 3 | Cycle 4 | Cycle 5 | Cycle 6 | Cycle 7 | Cycle 8 | Cycle 9 | ||
| Instruction 1 | IF | OF | EX | MEM | WB | |||||
| Instruction 2 | IF | OF | EX | MEM | MEM | MEM | WB | |||
| Instruction 3 | IF | OF | EX | Stall | Stall | MEM | WB | |||
The 5-stage pipeline has the following kinds of data hazard:
- An instruction in OF needs the result from an instruction in EX as a source operand. In this case, the EX instruction categories are load, store, multiply, divide, remainder, and floating-point instructions. This results in a 1–2 cycle stall.
- An instruction in OF uses the result from an instruction in MEM as a source operand. In this case, the MEM instruction categories are load, multiply, and floating-point instructions. This results in a 1 cycle stall.
Pipeline stalls are caused by data hazards, control hazards, structural hazards due to multi-cycle instructions, memory accesses using slower memory, instruction fetch from slower memory, or stream accesses.
The multi-cycle instruction categories are divide, remainder and floating-point instructions.