With C_OPTIMIZATION set to 3 (throughput), the pipeline is
divided into four stages to maximize computational throughput: fetch (IF), decode (OF),
execute (EX), and writeback (WB).
| Cycle 1 | Cycle 2 | Cycle 3 | Cycle 4 | Cycle 5 | Cycle 6 | Cycle 7 | Cycle 8 | |||
| Instruction 1 | IF | OF | EX | WB | ||||||
| Instruction 2 | IF | OF | EX | EX | EX | WB | ||||
| Instruction 3 | IF | OF | Stall | Stall | EX | WB | ||||
The 4-stage pipeline has the following data hazard:
- An instruction in OF needs the result from an instruction in EX as a source operand. In this case, the EX instruction categories are load, store, multiply, divide, remainder, and floating-point instructions. This results in a one cycle stall.
Pipeline stalls are caused by data hazards, control hazards, structural hazards due to multi-cycle instructions, memory accesses using slower memory, instruction fetch from slower memory, or stream accesses.
The multi-cycle instruction categories are divide, remainder and floating-point instructions.