With C_OPTIMIZATION set to 1 (area), the pipeline is divided
into three stages to minimize hardware cost: Fetch, Decode, and Execute.
| Cycle 1 | Cycle 2 | Cycle 3 | Cycle 4 | Cycle 5 | Cycle 6 | Cycle 7 | ||
| Instruction 1 | Fetch | Decode | Execute | |||||
| Instruction 2 | Fetch | Decode | Execute | Execute | Execute | |||
| Instruction 3 | Fetch | Decode | Stall | Stall | Execute | |||
The 3-stage pipeline does not have any data hazards. Pipeline stalls are caused by control hazards, structural hazards due to multi-cycle instructions, memory accesses using slower memory, instruction fetch from slower memory, or stream accesses.
The multi-cycle instruction categories are multiply, divide, remainder, and floating-point instructions.