Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504) - 2024.1 English

Document ID: UG1504
Release Date: 2024-06-19
Version: 2024.1 English

Introduction
About the Versal Adaptive SoC Design Methodology
Navigating Content by Design Process
About This Guide
System Design Types
System Design Types for Versal Devices without AI Engines
Hardware-Only System
Embedded System
System Design Types for Versal Devices with AI Engines
Embedded AI Engine System
System Design Planning Methodology Flow
Application Mapping and Design Partitioning
System Compute
Memory and Data Movement
Throughput and Latency
AI Engine Throughput and Latency
Simple Filter Chain Example
NoC Throughput and Latency
Power Requirements
Safety and Security Requirements
Performance Modeling and Simulation
Overview
Examples of Traffic Flow Scenarios
Performance Modeling in Vivado IP Integrator
DDR Memory Usage
HBM Memory Usage
Performance Modeling Examples and Tutorials
System Design Considerations
Hardware-Only System Design Considerations
Embedded System Design Considerations
Hardware and Software Compute Acceleration Development
Accelerator Hardware and Software Co-Design
Architecture
Datapath and Transport Layer
Control Plane
Memory Hierarchy
Software Development
Boot and OS
Software Application Development
AI Engine System Partitioning Planning
Methodology
Requirements Gathering
Algorithm Characteristics
System Requirements
Hardware Requirements
Solution Synthesis
Partitioning Validation
Iterate to System Feasibility
Example Use Case – Hough Transform
Requirements Gathering
Storage Requirements
Compute Requirements
I/O Bandwidth Requirements
Discussion on Vectorization and Lane Assignments
Solution Synthesis
Partitioning Validation
Iterate to System Feasibility
Power and Thermal Planning
Run Power Estimation
Define Thermal Design
Define Power Delivery
Define and Simulate PDN
Define Board and Use Schematic Checklist
Apply Constraints, Implement Design, and Report Power
Verify Design Constraints
System Debug Planning
Selecting the Debug Interfaces
Debug via JTAG
Debug via Aurora (HSDP)
Debug via PL Fabric
Debug via CPM PCIe Interface
Planning for AI Engine Debug
Planning for PS Debug
Planning for PL and Hard Block Debug
Planning for Software Debug
System Verification Planning
Simulation Recommendations
System Validation Planning
Hardware-Only System Validation Planning
Embedded System Validation Planning
Embedded AI Engine System Validation Planning
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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