Guidance messages when pipeline is not possible - 2024.1 English - XD261

Vitis Tutorials: Vitis HLS (XD261)

Document ID
XD261
Release Date
2024-06-19
Version
2024.1 English

At this point, you might think that we can also pipeline the outer loop, so let’s just add the pipeline pragma: there is a placeholder in the source code that you can uncomment. By the comments in the source code, you understand this is not possible, but why? Let’s see what messages Code Analyzer gives.

Code Analyzer process loop3 pipeline too much

After the code change and running C SIMULATION let’s see the output from Code Analyzer:

  1. The process table shows a guidance message relating to process loop3 : Some variables are accessed by more instructions than their hardware implementation can sustain in a single cycle, preventing some loops from being accelerated. Partition these variables to accelerate your design.

  2. We can expand the code of process loop3, to see what it relates to, along with other details.

  3. The overlay for the TI computations shows the word Details which is a clickable button, let’s click,

  4. A side information panel opens which shows the details about the II issue: too many accesses for the arrays.

Code Analyzer process loop3 pipeline too much

Comment out the pipeline pragma and keep only the pragma in the innermost-loop.